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目录

背景

目前为止，关于状态机独热码的题目，几乎没一个题目能做对，这令我疑惑？是不是题目的答案有问题？在此请大家一试？（已解决，谢谢）

我的做法

第一题

（点击蓝色字体进入题目链接做答）

本人答案：

module top_module (    input [6:1] y,    input w,    output Y2,    output Y4);        localparam A = 6'b0000_01, B = 6'b0000_10, C = 6'b0001_00, D = 6'b0010_00, E = 6'b0100_00, F = 6'b1000_00;    reg [6:1] next_state;    assign Y2 = next_state[2];    assign Y4 = next_state[4];    always@(*) begin        next_state = A;        case(y)            A: begin                if(w) next_state = A;                else next_state = B;            end            B: begin                if(w) next_state = D;                else next_state = C;            end            C: begin                if(w) next_state = D;                else next_state = E;            end            D: begin                if(w) next_state = A;                else next_state = F;            end            E: begin                if(w) next_state = D;                else next_state = E;            end            F: begin                if(w) next_state = D;                else next_state = C;            end        endcase    endendmodule

第二题

本人答案：

module top_module (    input [5:0] y,    input w,    output Y1,    output Y3);        localparam A = 6'b0000_01, B = 6'b0000_10, C = 6'b0001_00, D = 6'b0010_00, E = 6'b0100_00, F = 6'b1000_00;    reg [5:0] next_state;    assign Y1 = next_state[1];    assign Y3 = next_state[3];    always@(*) begin        case(y)            A: begin                if(~w) next_state = A;                else next_state = B;            end            B: begin                if(~w) next_state = D;                else next_state = C;            end            C: begin                if(~w) next_state = D;                else next_state = E;            end            D: begin                if(~w) next_state = A;                else next_state = F;            end            E: begin                if(~w) next_state = D;                else next_state = E;            end            F: begin                if(~w) next_state = D;                else next_state = C;            end            default: begin                next_state = A;            end        endcase    endendmodule

第三题

本人答案：

module top_module(    input in,    input [9:0] state,    output [9:0] next_state,    output out1,    output out2);        localparam S0 = 10'b0000_0000_01, S1 = 10'b0000_0000_10, S2 = 10'b0000_0001_00, S3 = 10'b0000_0010_00,S4 = 10'b0000_0100_00;     localparam S5 = 10'b0000_1000_00, S6 = 10'b0001_0000_00, S7 = 10'b0010_0000_00, S8 = 10'b0100_0000_00,S9 = 10'b1000_0000_00;    always@(*) begin        case(state)            S0: begin                if(in) next_state = S1;                else next_state = S0;            end            S1: begin                if(in) next_state = S2;                else next_state = S0;            end            S2: begin                if(in) next_state = S3;                else next_state = S0;            end            S3: begin                if(in) next_state = S4;                else next_state = S0;            end            S4: begin                if(in) next_state = S5;                else next_state = S0;            end            S5: begin                if(in) next_state = S6;                else next_state = S8;            end            S6: begin                if(in) next_state = S7;                else next_state = S9;            end            S7: begin                if(in) next_state = S7;                else next_state = S0;            end            S8: begin                if(in) next_state = S1;                else next_state = S0;            end            S9: begin                if(in) next_state = S1;                else next_state = S0;            end            default: begin               next_state = S0;             end                    endcase    end        assign out1 = (state == S8 | state == S9) ? 1 : 0;    assign out2 = (state == S9 | state == S7) ? 1 : 0;         endmodule

如有大神知道，还望告知，谢谢。

（崩溃中）

解决办法

更新：

群里的一个同学给我解答了，道理是有的，但是这个网站上有关独热码的题目真的没必要深究了，上面的设计本身就是没有问题的，仅仅为了正确的答案，给出Success的答案：

第一题

第一题：

module top_module (    input [6:1] y,    input w,    output Y2,    output Y4);        assign Y2 = y[1]&&(~w);    //assign Y4 = y[2]&&w || y[3]&&w || y[5]&&w || y[6]&&w;    assign Y4  = w&&(y[2] || y[3] || y[5] || y[6]);endmodule

第二题

第二题：

module top_module (    input [5:0] y,    input w,    output Y1,    output Y3);     assign Y1 = y[0]&& w;    assign Y3  = ~w && (y[1] || y[2] || y[4] || y[5]);endmodule

第三题

第三题：

module top_module(    input in,    input [9:0] state,    output [9:0] next_state,    output out1,    output out2);        assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]);    assign next_state[1] = in & (state[0] | state[8] | state[9]);    assign next_state[2] = in & state[1];    assign next_state[3] = in & state[2];    assign next_state[4] = in & state[3];    assign next_state[5] = in & state[4];    assign next_state[6] = in & state[5];    assign next_state[7] = in & (state[6] | state[7]);    assign next_state[8] = ~in & state[5];    assign next_state[9] = ~in & state[6];     assign out1 = state[8] | state[9];    assign out2 = state[7] | state[9];endmodule

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